PCIe M.2 — Key M Pinout
M.2 Key M is a 75-position Socket 3 connector mainly intended for storage modules. It can expose up to four PCIe lanes for NVMe devices or one SATA link, together with 3.3 V power and platform-management signals.
Compatibility warning: Key M describes the connector shape and pin map, not the interface, PCIe generation, lane count, or module length actually supported by the host. Always check both the host and drive documentation.
Connector overview
| Property | Value |
|---|---|
| Connector family | PCI Express M.2 / NGFF, Socket 3 |
| Key notch | Key M, positions 59 to 66 |
| Contacts | 75 positions; 67 electrical contacts with the Key M notch |
| Main use | NVMe PCIe SSDs and SATA SSDs |
| Possible host interfaces | PCIe x1, x2, or x4; SATA |
| Main supply | 3.3 V |
A Key M socket is commonly used for NVMe storage, but the key alone does not guarantee NVMe or SATA support. A B+M-keyed module may fit mechanically, although it is normally limited to the interfaces and two PCIe lanes available to that module.
Pinout diagram
Top side — odd pins
Bottom side — even pins
Pin assignment table
Signal names use the host/platform perspective: PET is transmitted by the host toward the module, while PER is received by the host from the module. SATA signal names are shown as their alternate functions on PCIe lane 0.
Color key: Power · Ground · PCIe / SATA · Management bus · Platform control
Top side
| Pin | Signal | Function |
|---|---|---|
| 1 / 3 | GND | Ground |
| 5 / 7 | PERn3 / PERp3 | PCIe lane 3, host receive pair |
| 9 | GND | Ground |
| 11 / 13 | PETn3 / PETp3 | PCIe lane 3, host transmit pair |
| 15 | GND | Ground |
| 17 / 19 | PERn2 / PERp2 | PCIe lane 2, host receive pair |
| 21 | GND | Ground |
| 23 / 25 | PETn2 / PETp2 | PCIe lane 2, host transmit pair |
| 27 | GND | Ground |
| 29 / 31 | PERn1 / PERp1 | PCIe lane 1, host receive pair |
| 33 | GND | Ground |
| 35 / 37 | PETn1 / PETp1 | PCIe lane 1, host transmit pair |
| 39 | GND | Ground |
| 41 / 43 | PERn0 / PERp0 or SATA-B+ / SATA-B− | PCIe lane 0 receive pair or SATA host receive pair |
| 45 | GND | Ground |
| 47 / 49 | PETn0 / PETp0 or SATA-A− / SATA-A+ | PCIe lane 0 transmit pair or SATA host transmit pair |
| 51 | GND | Ground |
| 53 / 55 | REFCLKn / REFCLKp | PCIe differential reference clock |
| 57 | GND | Ground |
| 59–66 | — | Mechanical Key M notch; no contacts |
| 67 | Reserved / no connect | Leave unconnected unless the applicable specification defines it |
| 69 | PEDET | Host interface detection: grounded by a SATA module and left open by a PCIe module |
| 71 / 75 | GND | Ground |
| 73 | GND or VIO_CFG | Ground in the conventional assignment; optional I/O-voltage configuration in supported revisions |
Bottom side
| Pin | Signal | Function |
|---|---|---|
| 2 / 4 | 3.3 V | Main module supply |
| 6 | PWRDIS or no connect | Optional power-disable control; availability depends on the specification revision |
| 8 | PLN# or no connect | Optional platform notification signal |
| 10 | DAS/DSS# / LED_1# | Device activity, staggered spin-up disable, or activity LED function |
| 12 / 14 / 16 / 18 | 3.3 V | Main module supply |
| 20 | Reserved / no connect | Leave unconnected unless defined by the applicable specification |
| 22 | VIO 1.8 V or no connect | Optional management-I/O supply |
| 24 / 26 / 28 | Reserved / no connect | Leave unconnected unless defined by the applicable specification |
| 30 | PLA_S3# or no connect | Optional platform sleep-state signal |
| 32 | Reserved / no connect | May be assigned with optional interfaces in newer specifications |
| 34 / 36 | USB_D+ / USB_D− or no connect | Optional USB 2.0 data pair in supported implementations |
| 38 | DEVSLP | SATA device-sleep control; may have another assignment with an optional interface |
| 40 | SMB_CLK | SMBus clock |
| 42 | SMB_DATA | SMBus data |
| 44 | ALERT# | Management-bus alert |
| 46 / 48 | Reserved / no connect | Leave unconnected unless defined by the applicable specification |
| 50 | PERST# | PCIe fundamental reset |
| 52 | CLKREQ# | PCIe reference-clock request |
| 54 | PEWAKE# | PCIe wake request |
| 56 / 58 | Reserved / no connect | Leave unconnected unless defined by the applicable specification |
| 59–66 | — | Mechanical Key M notch; no contacts |
| 68 | SUSCLK | Optional suspend clock |
| 70 / 72 / 74 | 3.3 V | Main module supply |
Signal groups
| Group | Pins | Notes |
|---|---|---|
| Power and ground | 2, 4, 12, 14, 16, 18, 70, 72, 74 and all GND pins | 3.3 V main supply and ground returns |
| PCIe lane 0 / SATA | 41, 43, 47, 49 | Shared differential pairs; the host selects PCIe or SATA operation |
| PCIe lanes 1–3 | 5, 7, 11, 13, 17, 19, 23, 25, 29, 31, 35, 37 | Three additional PCIe lanes for an x4 link |
| PCIe clock and control | 50, 52–55 | Reset, clock request, wake, and 100 MHz reference clock |
| Management bus | 40, 42, 44 | SMBus clock, data, and alert |
| Storage / platform control | 6, 8, 10, 30, 38, 68, 69 | Optional power, notification, activity, sleep, and interface-detection signals |
PCIe lane 0 and SATA are alternate functions on the same contacts. They cannot be used simultaneously by one module.
Electrical specifications
| Interface | Design value / requirement |
|---|---|
| Main power | Nominal 3.3 V on all specified supply contacts |
| PCIe pairs | 85 Ω differential nominal; place AC-coupling capacitors on each transmitter as required by PCIe |
| PCIe reference clock | 100 MHz differential clock when the common-clock architecture is used |
| SATA pairs | 100 Ω differential nominal |
| Management and control I/O | Logic level depends on the signal and specification revision; verify 1.8 V / 3.3 V compatibility |
| Active-low signals | Names ending in # are asserted low |
| Reserved / optional pins | Do not connect without confirming the current M.2 specification and both device datasheets |
Keep every high-speed pair short, impedance-controlled, and routed over a continuous reference plane. Match the two traces within each pair and avoid vias, stubs, plane gaps, and unnecessary layer changes.
Connector orientation
- The diagrams show the module contact edge, not the socket solder pads.
- The top/component side carries odd-numbered pins; the bottom side carries even-numbered pins.
- Pin 1 is at the end opposite pin 75. The Key M notch replaces positions 59–66, near pin 75.
- A socket footprint may appear mirrored compared with the module. Follow the connector manufacturer’s recommended PCB footprint.
Common wiring configurations
PCIe x4 NVMe SSD
- Route lanes 0 through 3, REFCLK, PERST#, CLKREQ#, and PEWAKE# as required by the platform.
- Connect every specified 3.3 V and ground contact; size the power rail for the drive’s peak current and thermal limits.
- Check the host’s supported PCIe generation, bifurcation rules, and boot support.
PCIe x2 or B+M-keyed SSD
- Route only the lane groups implemented by both the host and module.
- A B+M-keyed card can fit a Key M socket, but mechanical fit does not add the missing lanes or guarantee NVMe support.
SATA M.2 SSD
- Use the SATA alternate functions on pins 41, 43, 47, and 49.
- Implement PEDET and DEVSLP as required by the host and drive.
- Confirm that the socket supports SATA; many modern Key M sockets are PCIe-only.
Common mistakes
- Assuming that every Key M socket supports both NVMe/PCIe and SATA.
- Assuming that the M.2 card dimensions, such as 2230, 2242, 2260, or 2280, describe the electrical interface.
- Routing all four PCIe lanes when the host or module supports only x1 or x2.
- Swapping PET and PER because the signal names are read from the module perspective instead of the host perspective.
- Mirroring the footprint or confusing the top-side and bottom-side contact numbers.
- Using one generic logic voltage for every management and control signal.
- Connecting reserved pins based on an older or unrelated M.2 implementation.
- Ignoring SSD peak current, airflow, or thermal throttling.
Related connectors
| Connector | Typical use | Compatibility note |
|---|---|---|
| M.2 Key B / B+M | SATA, WWAN, PCIe x1/x2 | A B+M storage module may fit a Key M socket but remains limited by its own contacts and interfaces |
| M.2 Key A / A+E | Wireless connectivity | Different notch and pin assignment; not interchangeable with Key M |
| U.2 / U.3 | Cabled enterprise NVMe storage | Different connector and power arrangement; an appropriate adapter is required |
| SATA connector | 2.5-inch SATA storage | Same SATA protocol when supported, but different power and physical connector |
All PCIe M.2 pinout pages
Compatibility guide · Key A · Key A+E · Key B · Key B+A · Key B+E · Key B+M · Key E · Key M
Official specifications
- PCI Express M.2 specification overview — PCI-SIG
- PCI Express specifications — PCI-SIG
- NVM Express specifications — NVM Express
- Serial ATA specifications — SATA-IO
FAQ
Does every Key M SSD use NVMe?
No. Key M can carry PCIe/NVMe or SATA. Both the socket and the module must support the same interface.
Can a B+M-keyed SSD be installed in a Key M socket?
It can usually fit mechanically. Operation still depends on a shared interface, and a B+M PCIe module normally exposes no more than two PCIe lanes.
Does Key M always provide PCIe x4?
No. The pinout makes four lanes possible, but a host may wire fewer and a module may use fewer.
Do PCIe generation and NVMe version depend on the key?
No. The key does not identify the PCIe generation or NVMe revision. Check the host and drive specifications.
Is the connector hot-pluggable?
Do not assume it is. Power down the platform before inserting or removing a module unless the equipment documentation explicitly supports hot plugging.