Logic Level Compatibility Checker
Check CMOS and TTL logic level compatibility, calculate HIGH and LOW noise margins, and identify voltage mismatches between digital circuits.
Signal source
Current capability optional
Signal receiver
Current capability optional
Design conditions
Signal source → Signal receiver
- LOW output
- 0 V … 0.33 V
- HIGH output
- 2.97 V … 3.3 V
- Input LOW maximum VIL(max)
- 0.8 V
- Input HIGH minimum VIH(min)
- 2 V
- Minimum operating input VIN(min)
- 0 V
- Maximum operating input VIN(max)
- 5 V
- Absolute minimum input voltage
- -0.3 V
- Absolute maximum input voltage
- 5.3 V
One-way diagnosis
Insufficient data
HIGH noise margin
✓ Satisfied
LOW noise margin
✓ Satisfied
Verified criteria
- HIGH noise margin
- ✓ Satisfied
- LOW noise margin
- ✓ Satisfied
- Recommended input operating range
- ✓ Satisfied
- Absolute input limits
- ✓ Satisfied
Unverified criteria
- Current capability
- ? Not verified
Current capability: HIGH Not verified · LOW Not verified
Design conditions
All presets are illustrative assumptions, not device specifications. Replace every value with guaranteed datasheet limits at your supply, temperature and load. CMOS ratios are not universal. Presets leave currents unknown.
VCC is informational and never substitutes for pin limits. VIN(min/max) are recommended operating limits; absolute limits are stress ratings, never normal operating targets. Missing lower or upper bounds prevent a compatibility conclusion.
Only source → receiver is checked. Swap exchanges complete device profiles, including their separately entered input/output data; it does not convert output specifications into input specifications. Custom reverse data may be missing.
Use positive current magnitudes in mA, guaranteed at the entered VOH/VOL. Leave absent pull resistors blank. Leakage is a worst-case per-input bound; it is not added again to IIH/IIL. Pull-up voltage must include its supply tolerance. An unused current field may remain blank only if leakage bounds that input demand.
Static bounds at worst-case temperature, supply and load, with a common ground. Voltage uncertainty expands the output envelope in both directions and reduces both noise margins. Fan-out and pull loads are included; timing, transients, power sequencing and output contention are unverified.
NMH,eff = NMH − ΔV · NML,eff = NML − ΔV
VIN(min) ≤ VOL(min) − ΔV · VOH(max) + ΔV ≤ VIN(max)
IH = N · max(|IIH|, |II|) + max(0, VOH(max) + ΔV) / R↓
IL = N · max(|IIL|, |II|) + max(0, Vpull − VOL(min) + ΔV) / R↑Recommendations
- Compare guaranteed VIH/VIL, not nominal rails: a 3.3 V output can meet a 5 V TTL input's thresholds, while a 5 V CMOS input may require a higher HIGH level.
- Complete all unverified criteria before treating this connection as compatible. In particular, output extremes, recommended input limits, absolute limits and current data cannot be inferred from VCC.
- A static pass does not certify I²C, SPI, UART or any frequency. Check edges, propagation delay, setup/hold times, overshoot, ground offset and powered-off pins separately.