PCB Impedance Calculator
Analyse a controlled-impedance trace and check whether fabrication tolerances remain inside the target window.
Trace parameters
Stack-up cross-section
Quasi-static model
Calculated values
Fabrication assistant
Deterministic sweep of all 8 tolerance corners to anticipate production spread.
Pre-design estimate. Have the final width confirmed by the fabricator or a field solver using the actual stack-up, etch profile, solder mask and materials.
High-speed PCB guide
Turn a target impedance into a manufacturable specification
Controlled impedance depends on the complete stack-up, not trace width alone. Geometry, dielectric, copper, etch profile and manufacturing variation must be considered together.
Method and assumptions
The calculator applies single-ended quasi-static approximations for microstrip, embedded microstrip, symmetric/asymmetric stripline, dual stripline and coplanar waveguide. A numerical solver suggests the width matching the target, then the fabrication assistant evaluates all eight extreme combinations of width, dielectric height and εr.
Inputs to verify
Actual dielectric height
For microstrip, H is the trace-to-reference-plane distance. For symmetric stripline, the tool assumes the same height on both sides. Use the fabricator’s pressed thickness, not merely the nominal prepreg thickness.
Frequency-appropriate permittivity
Catalogue dielectric constant varies with resin content, frequency and measurement method. Prefer the design Dk supplied for the actual material and target frequency band.
Dual stripline: H1, C and H2
H1 separates the top plane from the first signal, C separates both signal layers, and H2 separates the second signal from the bottom plane. The tool calculates each layer’s single-ended impedance separately and uses their average for width synthesis.
Recommended workflow
- 1Choose the geometry and enter the fabricator’s proposed stack-up, including finished copper thickness.
- 2Set the single-ended target impedance and the tolerance required by the interface.
- 3Enter etch, height and εr tolerances, then give the fabricator the impedance target rather than freezing a width when they provide impedance control.
Decision example
A nominal 50 Ω trace can leave a ±10% window when dielectric is 10% thicker and etching is 25 µm narrower. The tolerance envelope exposes that risk before stack-up review with the fabricator.
Why a field solver is still needed
Closed-form equations do not precisely model solder mask, copper roughness, trapezoidal etching, glass weave, nearby planes, vias or frequency dispersion. Displayed corners are a deterministic envelope, not a statistical distribution or yield guarantee.
Frequently asked questions
Should the calculated width be imposed on the fabricator?
Not necessarily. For an impedance-controlled order, provide target, tolerance and affected layers. The fabricator often adjusts width and dielectric using its actual materials and process.
Does solder mask change impedance?
Yes, especially for narrow microstrips: part of the field crosses the mask and impedance generally decreases. Include mask thickness and Dk in final validation.
References to consult
- E. O. Hammerstad and Ø. Jensen, Accurate Models for Microstrip Computer-Aided Design, IEEE MTT-S, 1980.
- IPC-2141A, Design Guide for High-Speed Controlled Impedance Circuit Boards.
- IPC-6012 qualification and performance requirements for rigid printed boards, supplemented by fabricator coupons and rules.
Original educational content, reviewed for technical clarity on 13 September 2026. Always verify datasheets, applicable standards, and your design before power-up or manufacture.