PCB Via Calculator
Calculate allowable continuous current for a parallel via group from its geometry, thermal environment, and requested temperature rise.
Electrical and thermal parameters
Plated through-hole across the complete board thickness.
Use a simulation, a measurement, or fabricator-validated rule that includes planes and adjacent copper.
First-order coaxial approximation for the via group. Use the actual stack-up antipad and εr; validate fast links through EM extraction.
Electrical via cross-section
Electro-thermal model
The path is a through barrel. Enter its actual finished conductive length rather than the nominal layer count.
Electrical results
High-frequency results
Thermal compatibility
IPC / fabricator validation required
A green status only confirms compatibility with entered limits; it is not IPC compliance or fabrication qualification.
Continuous-operation pre-sizing estimate. Thermal resistance must represent the via group, nearby copper, planes, actual stack-up, and cooling. Check IPC-2221, IPC-6012, and fabricator rules before approving allowable current, temperature rise, reliability, or fabrication constraints. The LC quantities use a first-order coaxial model: they guide pre-sizing but do not replace actual antipads, stubs, or 3D electromagnetic simulation.
PCB fabrication guide
Choose and pre-size a via without hiding HDI constraints
A via is both an electrical connection and a fabrication operation. Its type sets the process; plated length, finished drill, barrel copper, parallel paths, antipad, and thermal environment determine its loss and high-frequency behaviour.
Method and assumptions
The tool calculates plated-path resistance from its length, finished drill, and barrel copper. It applies copper’s temperature-dependent resistivity, then solves the current that reaches the requested maximum rise without exceeding the allowed maximum via temperature. For high frequency, it uses a first-order coaxial approximation from antipad, εr, and length to estimate C, L, resonance, and impedance — not as a replacement for EM extraction.
Inputs to verify
Via type and actual plated length
The via type indicates process constraints, but the electrical calculation needs the actual finished length travelled by copper. For a stacked microvia, enter the sum of stage lengths and their count to visualise the depth per transition.
Finished dimensions, not CAD dimensions alone
Use the finished drill and finished barrel copper specified by the fabricator. Tool diameter before plating and deposited barrel copper vary from one process to another, and directly change conductor area.
Electrical connection between two layers
The tool represents an electrical connection between two layers. Actual plated length remains the quantity governing the electrical, thermal, and high-frequency models, including any through-via stub.
Antipad, εr, and frequency
For LC values, use the real clearance diameter in the reference plane and the stack-up dielectric permittivity. Displayed reactance is for the lumped RLC model at the analysis frequency; it is not an S-parameter for the complete via.
Target rise, parallel paths, and thermal resistance
Do not enter current: the tool calculates allowable continuous current at the target temperature rise. Count as parallel only paths fed symmetrically. Enter a thermal resistance representing the complete via group, pads, planes, stack-up, and cooling; it cannot be derived from drill geometry alone.
Recommended workflow
- 1Choose the via mode, then take finished conductive length, drill, and barrel copper from the fabricator’s stack-up and DFM documentation.
- 2Enter paths that actually share current, ambient temperature, the target maximum rise, and the allowed maximum temperature. The tool derives allowable continuous current.
- 3Enter antipad, εr, and frequency to place capacitance, inductance, resonance, and reactance in context, then confirm fast links through analysis or testing.
Reading example
For a 1 mm plated length, 0.30 mm finished drill, and 25 µm barrel copper, 20 °C resistance is about 0.675 mΩ. With a group thermal resistance of 100 °C/W and a 10 °C target rise, the tool calculates the current that brings the group to that rise. Change that resistance to reflect your actual copper and cooling.
What the calculation does not validate
The model does not derive thermal resistance from via geometry and does not know drill profile, copper fill, lamination cycles, or reliability coupons. Green only means the entered thermal limits are mutually compatible; it does not certify IPC compliance or fabrication capability. LC values are a lumped approximation: they do not faithfully model stubs, return current, non-circular antipads, discontinuities, dielectric loss, or S-parameters. Those cases require a 3D EM solver or measurement.
Frequently asked questions
What should I check for a stacked microvia?
Stacking keeps a compact connection axis, but often needs controlled filling and cap plating. Check HDI rules, lamination cycles, reliability target, and the fabricator’s explicit capabilities.
Can I use a generic thermal resistance?
Only for very early option comparison. Thermal resistance varies greatly with copper planes, via density, PCB thickness and materials, airflow, and nearby heat sources. For a current decision, use a simulated, measured, or fabricator-provided value.
Is the displayed maximum current a fabrication specification?
No. It is the point where the model reaches your target temperature rise with the entered thermal resistance while respecting the allowed maximum temperature. It is a continuous-design reference; a production limit still requires fabricator rules and, for a critical function, thermal and reliability validation.
Is the calculated impedance enough for a fast link?
No. It gives a trend from a simplified coaxial geometry. A real fast transition includes pads, antipads, stubs, return current, and coupling: check it with S-parameters, 3D simulation, or a measurement coupon.
References to consult
- IPC-2152, guidance on printed-board conductor current capacity and temperature rise; complement it with the real thermal environment.
- IPC-2221, generic printed-board design requirements, including drilling, pad, and annular-ring principles.
- IPC-6012 and IPC-6013, performance and qualification specifications for rigid and rigid-flex boards, complemented by fabricator capabilities.
- The selected fabricator’s stack-up, DFM guide, and HDI rules: they always take precedence over a generic rule.
- Analog Devices and Texas Instruments notes on via parasitics and high-frequency discontinuities; supplement them with EM extraction of the actual stack-up.
Original educational content, reviewed for technical clarity on 14 September 2026. Always verify datasheets, applicable standards, and your design before power-up or manufacture.