Logic Level Compatibility: CMOS, TTL, Voltage Thresholds and Noise Margins
Learn how to compare VOH, VOL, VIH and VIL thresholds, calculate noise margins, and safely interface 1.8 V, 3.3 V and 5 V digital circuits.
Digital pins exchange voltage ranges, not ideal zeroes and ones. A connection needs valid logic, acceptable pin voltages and enough drive current under the same supply, temperature and load conditions. Use the Logic Level Compatibility Checker for one direction at a time. The numerical examples below are illustrative design assumptions, not specifications of a named device.
1. Digital logic levels
A receiver recognizes LOW below its guaranteed VIL(max) and HIGH above VIH(min), within its operating range. Between these thresholds the logic state is undefined. A signal resting there may increase supply current or cause multiple transitions. A nominal 3.3 V supply alone says nothing about guaranteed pin levels, input tolerance or power-off behavior. Include ground offset in the voltage budget.
2. TTL and CMOS
Traditional TTL uses bipolar circuitry; CMOS uses complementary MOS transistors. Input thresholds, loading and output swing vary by family. A 5 V TTL input often specifies VIH = 2 V and VIL = 0.8 V; this is not a specification for every 5 V input. Some CMOS families use supply-related thresholds, while HCT uses TTL-compatible thresholds. The calculator's 0.7/0.3 input ratios and 0.9/0.1 output ratios are editable illustrations, never universal CMOS guarantees.
3. Reading VOH, VOL, VIH and VIL
| Parameter | Guaranteed meaning |
|---|---|
| VOH(min) | Lowest HIGH output at the specified source current |
| VOL(max) | Highest LOW output at the specified sink current |
| VIH(min) | Minimum input voltage guaranteed to be read as HIGH |
| VIL(max) | Maximum input voltage guaranteed to be read as LOW |
Do not mix typical values with worst-case limits. VOH(min) does not bound the maximum output voltage. Enter VOH(max) and VOL(min) independently, including supply tolerance or other documented constraints. Keep the output-current test conditions consistent with the chosen voltage guarantees.
4. HIGH and LOW noise margins
NMH = VOH(min) − VIH(min) and NML = VIL(max) − VOL(max).
A negative margin proves a logic mismatch. Zero is a boundary with no noise allowance. A positive margin below the configurable warning threshold is marginal. The optional output uncertainty ΔV reduces both margins: NMH,eff = NMH − ΔV, NML,eff = NML − ΔV. Use guaranteed supply corners first; do not count the same uncertainty twice. One volt equals 1000 millivolts.
5. Operating limits and absolute ratings
Logic recognition thresholds are separate from recommended input operating limits and absolute maximum ratings. Require VOL(min) − ΔV ≥ VIN(min) and VOH(max) + ΔV ≤ VIN(max) for operation, then check the independently entered absolute limits. Passing stress limits does not establish normal operation. Every known output bound is checked, so even incomplete data can reveal a violation; an absent bound prevents a complete pass. Absolute ratings describe stress limits, not safe operating targets. Check overshoot, undershoot, injection current and pin-specific 5 V tolerance separately. A powered-off receiver may have different constraints.
6. Example: 3.3 V output to 5 V TTL input
Assume VOH(min) = 2.9 V, VOL(max) = 0.2 V, VIH(min) = 2.0 V and VIL(max) = 0.8 V. Then NMH = 2.9 − 2.0 = 0.9 V = 900 mV and NML = 0.8 − 0.2 = 0.6 V = 600 mV. Both exceed a 0.1 V warning threshold. With an output envelope of 0–3.6 V, a documented input operating range of 0–5 V and absolute limits of −0.3–5.5 V, the voltage checks also pass at ΔV = 0. If HIGH/LOW drive capabilities are each 4 mA, input demands are 0.02/0.4 mA, fan-out is one and pull resistors are absent, current passes. Only with all these guarantees can the static result be compatible; missing current data yields insufficient data.
7. Example: 5 V output to non-tolerant 3.3 V input
Assume VOH(min) = 4.4 V, VOL(max) = 0.4 V, VIH(min) = 2.31 V and VIL(max) = 0.99 V. NMH = 4.4 − 2.31 = 2.09 V, NML = 0.99 − 0.4 = 0.59 V: logic margins are positive. But an output maximum of 5.25 V exceeds both a 3.3 V operating maximum and a 3.6 V absolute maximum. The result is incompatible regardless of the favorable margins. A series resistor alone does not establish voltage tolerance; clamping, injection limits and power states require device-specific analysis.
8. Example: CMOS versus TTL thresholds
Take the 2.9/0.2 V CMOS output from example 1 and a 5 V CMOS receiver with VIH = 3.5 V and VIL = 1.5 V. NMH = 2.9 − 3.5 = −0.6 V, while NML = 1.5 − 0.2 = 1.3 V. HIGH fails although the same source met the TTL input. Conversely, an illustrative TTL source with VOH(min) = 2.4 V and VOL(max) = 0.4 V driving that CMOS input gives NMH = −1.1 V and NML = 1.1 V. Changing direction requires the real reverse input/output specifications, not simply swapping threshold names.
9. Choosing level translation
Use a direction-controlled translator or a buffer specified for both voltage domains when appropriate. Transistor circuits and resistor dividers have load, edge-rate and inversion constraints. A divider can suit a unidirectional, sufficiently slow input after RC settling and protection currents are checked; it does not suit every fast or bidirectional interface. Start with the voltage-divider calculator and verify the loaded circuit. A dedicated translator still needs compatible pin limits, enable sequencing and timing.
10. Push-pull, open-drain and current
Push-pull actively sources and sinks current. Open-drain actively sinks LOW and releases HIGH to a pull-up; its HIGH is a property of the complete bus, not the output's VCC. The checker does not solve that bus voltage. A MOSFET translator may suit certain open-drain buses, but must be selected for the actual voltages, capacitance and timing.
The static current model uses positive magnitudes: IH = N × max(|IIH|, |II|) + max(0, VOH(max) + ΔV) / Rdown and IL = N × max(|IIL|, |II|) + max(0, Vpull − VOL(min) + ΔV) / Rup. V divided by kΩ gives mA. Leakage is an alternative bound on the same input demand and is not double-counted. Leave absent resistors blank; enter actual zero input demand explicitly. These conservative pull-load bounds check drive at the entered VOH/VOL, not short-circuit current. Use the pull-up / pull-down calculator for resistor selection and rise time. Neither static calculation certifies an I²C speed.
11. Scope and limitations
Incompatible means at least one checked criterion fails. Otherwise unknown essential voltage or current data yields insufficient data. With complete checks, zero or small margins yield marginal; all other static checks passing yields compatible. The tool assumes a common ground and guaranteed loaded output envelopes. It does not simulate edges, ringing, capacitive current, hysteresis, contention, power sequencing, injection or reliability. SPI and UART require their own timing budgets. See the PCB transmission-line guide for interconnect effects.
12. Technical FAQ
Does 3.3 V always work with 5 V?
No. Example 1 meets the assumed TTL thresholds, while example 3 fails the assumed CMOS HIGH threshold. Check the exact receiver datasheet.
Are positive margins enough?
No. Example 2 has positive margins but exceeds the voltage limits. Current and all essential voltage bounds must also be verified.
Can I use absolute maximum ratings as input limits?
Enter them only in the separate absolute fields. Use recommended conditions for VIN(min/max). Operation between those ranges is not a normal operating pass.
Why does a preset show insufficient data?
Its currents are intentionally unknown, and every voltage is only illustrative. Replace the assumptions with guaranteed device values; fill the missing criteria before drawing a conclusion.
Does swapping verify a bidirectional interface?
It swaps full device profiles and performs another one-way calculation. It preserves separately entered specifications. Custom profiles may lack reverse data; each direction and each bus driver needs independent checking.
Does a pass guarantee a protocol or frequency?
No. Validate rise/fall times, loading, setup/hold, propagation, ground offsets and power states. For open-drain buses also check every pull-up and sink path.
13. Verified manufacturer references
- Texas Instruments SZZA036C — Understanding and Interpreting Standard-Logic Data Sheets: definitions, test conditions and rating categories.
- Texas Instruments SN74LVC1G125 datasheet: example of a buffer with documented overvoltage-tolerant inputs; inspect operating and power-off conditions.
- Texas Instruments SN74LS00 datasheet: real TTL thresholds and current-dependent output guarantees.
- Texas Instruments SLVA689 — I²C Bus Pull-Up Resistor Calculation: pull resistance, sink current, bus capacitance and rise time.