How to Calculate Crystal Load Capacitors — Complete Design Guide
Learn how to calculate crystal load capacitance, select oscillator capacitors, account for PCB parasitics, and design reliable crystal oscillator circuits.
Crystal Load Capacitor Calculator →
Quartz oscillators
A quartz resonator converts electrical energy into mechanical vibration and back through the piezoelectric effect. In a Pierce oscillator, the MCU amplifier supplies energy while the resonator selects the operating region. This calculator sizes the capacitive network; it does not model the complete active oscillator.
Series and parallel resonance
The motional inductance and capacitance resonate at the series frequency fs. The electrode shunt capacitance C0 creates a higher antiresonant frequency. A parallel-load crystal is calibrated for a specified external load between these frequencies. A series-specified crystal cannot be substituted solely on the basis of its marked frequency.
What CL means
CL is the equivalent external capacitance seen between the crystal terminals at the specified operating frequency. It is given in the crystal datasheet. It is neither the value of each external capacitor nor the crystal’s own shunt capacitance C0. Start with the specified CL, rather than a customary 18 pF or 22 pF component.
The role of C1 and C2
Each capacitor connects one oscillator pin to the local ground. Seen between the crystal terminals, their path through ground forms a series combination. Equal values simplify selection, but unequal values are valid in the load model. Deliberate asymmetry also affects the active oscillator and must follow the MCU guidance.
PCB and MCU parasitics
In simple mode, Cstray is one equivalent total contribution. It is not the arithmetic sum of all pin capacitances. Advanced mode puts Cpin1 and Cpin2 on their respective branches and adds only the remaining equivalent Cpcb. Read the pin specifications and include any enabled internal load bank in the appropriate branch. Do not count a contribution in both models.
Deriving the equations
For the series path, Q = C1 V1 = C2 V2 and V = V1 + V2. Therefore 1/Cseries = 1/C1 + 1/C2. Adding the equivalent stray contribution gives the first equation below. With C1 = C2 = C, the series term is C/2; rearranging yields C = 2(CL − Cstray). For the advanced model, set T = CL − Cpcb, A = Cpin1 and B = Cpin2. Expanding gives x² + (A + B − 2T)x + AB − T(A + B) = 0. The non-negative root below is the common external value x. If T is below the pin-only series contribution, no solution exists.
Worked example: 12.5 pF load
With CL = 12.5 pF and Cstray = 3 pF, C1 = C2 = 2 × 9.5 = 19 pF. The nearest E12 value is 18 pF, giving CL = 9 + 3 = 12 pF, an error of −0.5 pF (−4%). E24 has a tie between 18 and 20 pF; this tool chooses the lower value. The alternative 20 pF gives 13 pF, or +0.5 pF (+4%). These percentages describe capacitance error, not frequency error. In advanced mode with Cpcb = 1 pF and both pins = 2 pF, 21 pF external capacitors produce (23/2) + 1 = 12.5 pF.
RTC example: 32.768 kHz
Assume a 32.768 kHz crystal specified at CL = 7 pF and an estimated Cstray = 2 pF. The required pair is 10 pF each, available in E12 and E24; the calculated load is 5 + 2 = 7 pF. These are example assumptions, not universal RTC values. Check the selected RTC’s internal load settings before adding external capacitors. The frequency does not enter the capacitance equation.
How load error shifts frequency
For a fundamental parallel-load crystal, increasing CL generally lowers the frequency toward fs; reducing CL generally raises it. The approximate relation below uses the motional capacitance Cm and shunt capacitance C0. Without those parameters or the crystal’s pullability data, a pF mismatch cannot be converted reliably into ppm. Temperature, ageing and initial tolerance add separate errors.
PCB layout
Place the crystal and load capacitors close to the MCU pins. Keep traces short and the oscillator loop compact. Route fast clocks, switching nodes and noisy buses away from XIN and XOUT. Control coupling to adjacent traces and copper, and use short ground returns. Follow the MCU’s specific rules for planes, guard structures and keepouts; additional copper changes the parasitic capacitance.
Common sizing mistakes
Avoid setting each capacitor equal to CL, ignoring pin loading, counting stray capacitance twice, or treating an E-series rounded value as an exact match. Use stable dielectric capacitors such as C0G/NP0 where appropriate and account for tolerance. E12/E24 identify preferred values, not guaranteed availability or a guaranteed tolerance. Probing an oscillator adds capacitance and can alter its operation.
Limits and prototype checks
This model omits amplifier gain, crystal ESR, negative resistance, startup margin, excitation power (drive level), nonlinear behaviour and component variation. A matching load alone proves none of these. Validate startup and drive level on the actual board over the specified supply and temperature ranges, using the crystal and MCU datasheets. Keep adequate margin for tolerances and production spread.
Choosing a calculation mode
| Use case | Inputs | Check |
|---|---|---|
| New symmetric design | CL and equivalent Cstray | Equal C1/C2 and E12/E24 load error |
| Existing board | C1, C2, Cstray; optional nominal CL | Actual load and mismatch |
| Known MCU pin loading | CL, Cpcb, Cpin1, Cpin2 | External capacitance and physical feasibility |
Technical FAQ
Why are the external capacitors about twice CL?
The pair acts in series, so equal capacitors contribute C/2. Subtract the equivalent stray term before multiplying by two.
Can C1 and C2 differ?
Yes. Actual-load mode calculates their series contribution. Check the MCU manufacturer’s requirements before choosing an asymmetric network.
Does 16 MHz require a different formula from 32.768 kHz?
No. The load equation is the same. The crystal parameters and oscillator startup and drive requirements can be very different.
What if CL is lower than the parasitics?
Adding positive external capacitance cannot reach the requested load. Recheck the model and pin specifications or choose a compatible crystal or oscillator configuration.
Does an exact CL match guarantee startup?
No. Startup also depends on ESR, negative resistance, amplifier conditions, drive settings and the physical layout.
Can I infer ppm error from the displayed percentage?
No. The displayed percentage is a capacitance difference. Frequency pulling requires crystal-specific parameters or measurements.
Official technical references
Related tools and guides
Design estimates only. Matching CL does not guarantee oscillator startup or stability. Check ESR, negative resistance, drive level and tolerances.