PCIe M.2 — Key A Pinout
M.2 Key A is a 75-position Socket 1 connector mainly intended for wireless and connectivity modules. It can expose two independent PCIe links, USB 2.0, four DisplayPort lanes, I²C, and platform control signals.
Compatibility warning: Key A describes the connector shape and pin map, not the interfaces actually wired by the host. Always check both the host and module documentation.
Connector overview
| Property | Value |
|---|---|
| Connector family | PCI Express M.2 / NGFF, Socket 1 |
| Key notch | Key A, positions 8 to 15 |
| Contacts | 75 positions; 67 electrical contacts with the Key A notch |
| Main use | Wi-Fi, Bluetooth, NFC, GNSS, WiGig, and other connectivity modules |
| Possible host interfaces | 2 × PCIe x1, USB 2.0, DisplayPort x4, I²C |
| Main supply | 3.3 V |
Key A is not the usual connector for an M.2 NVMe SSD. Storage devices normally use Key M or Key B+M.
Pinout diagram
Top side — odd pins
Bottom side — even pins
Pin assignment table
Signal names use the host/platform perspective: PET is transmitted by the host toward the module, while PER is received by the host from the module.
Color key: Power · Ground · USB · PCIe · DisplayPort · I²C · Radio control
Top side
| Pin | Signal | Function |
|---|---|---|
| 1 | GND | Ground |
| 3 | USB_D+ | USB 2.0 positive data |
| 5 | USB_D− | USB 2.0 negative data |
| 7 | GND | Ground |
| 8–15 | — | Mechanical Key A notch; no contacts |
| 17 | DP_MLDIR | DisplayPort main-link direction control |
| 19 / 21 | DP_ML3n / DP_ML3p | DisplayPort lane 3 |
| 23 | GND | Ground |
| 25 / 27 | DP_ML2n / DP_ML2p | DisplayPort lane 2 |
| 29 | GND | Ground |
| 31 | DP_HPD | DisplayPort hot-plug detect |
| 33 | GND | Ground |
| 35 / 37 | PETp0 / PETn0 | PCIe link 0, host transmit pair |
| 39 | GND | Ground |
| 41 / 43 | PERp0 / PERn0 | PCIe link 0, host receive pair |
| 45 | GND | Ground |
| 47 / 49 | REFCLKp0 / REFCLKn0 | PCIe link 0 reference clock |
| 51 | GND | Ground |
| 53 | CLKREQ0# | PCIe link 0 clock request |
| 55 | PEWAKE0# | PCIe link 0 wake request |
| 57 | GND | Ground |
| 59 / 61 | PETp1 / PETn1 | PCIe link 1, host transmit pair |
| 63 | GND | Ground |
| 65 / 67 | PERp1 / PERn1 | PCIe link 1, host receive pair |
| 69 | GND | Ground |
| 71 / 73 | REFCLKp1 / REFCLKn1 | PCIe link 1 reference clock |
| 75 | GND | Ground |
Bottom side
| Pin | Signal | Function |
|---|---|---|
| 2 / 4 | 3.3 V | Main module supply |
| 6 | LED_1# | Open-drain status LED control |
| 8–15 | — | Mechanical Key A notch; no contacts |
| 16 | LED_2# | Open-drain status LED control |
| 18 | VIO_CFG | I/O-voltage configuration input |
| 20 / 22 | DP_AUXn / DP_AUXp | DisplayPort auxiliary channel |
| 24 | GND | Ground |
| 26 / 28 | DP_ML1n / DP_ML1p | DisplayPort lane 1 |
| 30 | GND | Ground |
| 32 / 34 | DP_ML0n / DP_ML0p | DisplayPort lane 0 |
| 36 | GND | Ground |
| 38 / 40 / 42 | Vendor-defined | Use only when documented by both devices |
| 44 | COEX3 | Wireless coexistence control |
| 46 | COEX_RXD | Wireless coexistence receive |
| 48 | COEX_TXD | Wireless coexistence transmit |
| 50 | SUSCLK | Suspend clock |
| 52 | PERST0# | PCIe link 0 reset |
| 54 | W_DISABLE2# | Wireless function 2 disable |
| 56 | W_DISABLE1# | Wireless function 1 disable |
| 58 | I2C_DATA | I²C data |
| 60 | I2C_CLK | I²C clock |
| 62 | ALERT# | I²C / platform alert |
| 64 | VIO 1.8 V | 1.8 V I/O supply |
| 66 | PERST1# | PCIe link 1 reset |
| 68 | CLKREQ1# | PCIe link 1 clock request |
| 70 | PEWAKE1# | PCIe link 1 wake request |
| 72 / 74 | 3.3 V | Main module supply |
Signal groups
| Group | Pins | Notes |
|---|---|---|
| Power and ground | 2, 4, 64, 72, 74 and all GND pins | 3.3 V main supply, 1.8 V I/O supply, and ground returns |
| I/O configuration | 18 | Platform-specific I/O-voltage configuration input |
| USB 2.0 | 3, 5 | One bidirectional USB 2.0 link, often used by Bluetooth |
| PCIe link 0 | 35, 37, 41, 43, 47, 49, 52, 53, 55 | One PCIe x1 link with reference clock, reset, clock request, and wake |
| PCIe link 1 | 59, 61, 65, 67, 66, 68, 70, 71, 73 | A second independent PCIe x1 link |
| DisplayPort | 17, 19–22, 25–28, 31–34 | Four main lanes, AUX channel, HPD, and direction control |
| I²C | 58, 60, 62 | 1.8 V management bus and alert |
| Radio control | 6, 16, 44, 46, 48, 50, 54, 56 | LEDs, disable controls, suspend clock, and coexistence |
The two PCIe groups are normally treated as independent x1 links. Do not assume that the host combines them into one x2 link.
Electrical specifications
| Interface | Design value / requirement |
|---|---|
| Main power | Nominal 3.3 V on pins 2, 4, 72, and 74 |
| Management I/O | 1.8 V VIO on pin 64; confirm every control-signal level in the module specification |
| PCIe pairs | 85 Ω differential nominal; place AC-coupling capacitors on each transmitter as required by PCIe |
| PCIe reference clock | 100 MHz differential clock when the clocked architecture is used |
| USB 2.0 pair | 90 Ω differential nominal |
| DisplayPort pairs | 100 Ω differential nominal |
| Active-low signals | Names ending in # are asserted low |
| Unused / vendor pins | Leave unconnected unless the host and module documentation defines them |
Keep high-speed pairs short, length-matched where required, on a continuous reference plane, and away from gaps, switching nodes, and connector mounting holes.
Connector orientation
- The diagrams show the module contact edge, not the socket solder pads.
- The top/component side carries odd-numbered pins; the bottom side carries even-numbered pins.
- Pin 1 is at the end opposite pin 75. The Key A notch replaces positions 8–15 near pin 1.
- A socket footprint may appear mirrored compared with the module. Follow the connector manufacturer’s recommended PCB footprint.
Common wiring configurations
Wi-Fi plus Bluetooth module
- Use PCIe link 0 for Wi-Fi and USB 2.0 on pins 3 and 5 for Bluetooth.
- Connect 3.3 V, every specified ground, PERST0#, CLKREQ0#, and PEWAKE0#.
- Route W_DISABLE# and LED# only when required by the product.
Two-radio connectivity module
- Use PCIe link 0 and link 1 as two independent x1 connections.
- Keep each link’s clock, reset, clock-request, and wake signals with the matching link number.
DisplayPort connectivity module
- Route all required main lanes, AUX, HPD, and DP_MLDIR.
- Check lane count, lane mapping, polarity inversion support, and AUX voltage requirements in both datasheets.
I²C-managed module
- Connect I2C_DATA, I2C_CLK, ALERT#, and the correct 1.8 V I/O domain.
- Fit pull-ups only as specified by the platform; duplicated pull-ups can make the bus too strong.
Common mistakes
- Assuming that any physically fitting M.2 card is electrically compatible.
- Plugging a Key M or B+M SSD into a Key A connectivity socket.
- Treating the two PCIe x1 links as a guaranteed x2 link.
- Swapping PET and PER because the signal names are read from the module perspective instead of the host perspective.
- Mirroring the footprint or confusing the top-side and bottom-side contact numbers.
- Powering 1.8 V management signals from 3.3 V without checking tolerance.
- Connecting vendor-defined pins or relying on hot-plug operation without explicit support.
Related connectors
| Connector | Typical use | Compatibility note |
|---|---|---|
| M.2 Key E | Wireless connectivity | Dual-key A+E modules may fit either socket, but only shared, wired interfaces will work |
| M.2 Key B | WWAN, SATA, PCIe x2 | Different notch and pin assignment; not directly interchangeable |
| M.2 Key M | NVMe SSD, PCIe x4 | Storage-oriented connector; not compatible with Key A |
| Mini PCI Express | Older wireless cards | Different 52-pin connector and pinout; an active adapter may be required |
All PCIe M.2 pinout pages
Compatibility guide · Key A · Key A+E · Key B · Key B+A · Key B+E · Key B+M · Key E · Key M
Official specifications
- PCI Express M.2 specification overview — PCI-SIG
- PCI Express specifications — PCI-SIG
- USB specifications and documents — USB-IF
- DisplayPort standards — VESA
- I²C-bus specification and user manual — NXP
FAQ
Can a Key E module be installed in a Key A socket?
Only a module with a compatible A+E edge key can physically fit both. Electrical operation still depends on the interfaces wired by the host and used by the module.
Can a Key A socket accept an NVMe SSD?
Normally no. NVMe SSDs generally use Key M or B+M and require a storage-oriented socket.
Are both PCIe links always available?
No. The pinout provides two independent PCIe link groups, but a host may wire one, both, or neither.
Can every interface be used simultaneously?
Not necessarily. Some pins are dedicated, but actual combinations depend on the platform and module implementation.
Is the connector hot-pluggable?
Do not assume it is. Power down the platform before inserting or removing a module unless the equipment documentation explicitly supports hot plugging.