PCIe M.2 — Key B+M Pinout
An M.2 Key B+M module has both the B and M notches so that it can fit mechanically in compatible Key B and Key M sockets. This dual-key arrangement is mainly used by SATA SSDs and PCIe/NVMe devices with up to two PCIe lanes.
Compatibility warning: B+M describes the module’s two mechanical notches, not a distinct socket or a guaranteed interface. The host socket must support the same SATA or PCIe interface as the module, and a B+M PCIe module cannot use all four lanes of a Key M socket.
Connector overview
| Property | Value |
|---|---|
| Connector family | PCI Express M.2 / NGFF storage-module edge |
| Key notches | Key B, positions 12 to 19; Key M, positions 59 to 66 |
| Contacts | 75 positions; 59 electrical contacts with both notches |
| Compatible sockets | Mechanically compatible with suitable Socket 2 Key B and Socket 3 Key M connectors |
| Main use | SATA SSDs and PCIe/NVMe x1 or x2 SSDs |
| Possible interfaces | One SATA link or PCIe x1/x2; SMBus and storage-control signals |
| Main supply | 3.3 V |
There is no separate “B+M socket” in the usual M.2 connector family. The dual notches are placed on the module to broaden mechanical compatibility. They do not combine every Key B and Key M interface.
Pinout diagram
Top side — odd pins
Bottom side — even pins
Pin assignment table
Signal names use the host/platform perspective: PET is transmitted by the host toward the module, while PER is received by the host from the module. SATA signal names are shown as alternate functions on PCIe lane 0.
Color key: Power · Ground · PCIe / SATA · Management bus · Storage / platform control
Top side
| Pin | Signal | Function |
|---|---|---|
| 1 | GND / CONFIG_3 | Ground; also identifies the module configuration to a Key B host |
| 3 | GND | Ground |
| 5 / 7 / 9 / 11 | Reserved / no connect | Not used by the conventional B+M storage pinout |
| 12–19 | — | Mechanical Key B notch; no contacts |
| 21 | GND / CONFIG_0 | Ground; also used as a module-configuration strap by a Key B host |
| 23 / 25 | Reserved / no connect | Leave unconnected unless the module documentation defines them |
| 27 | GND | Ground |
| 29 / 31 | PERn1 / PERp1 | PCIe lane 1, host receive pair |
| 33 | GND | Ground |
| 35 / 37 | PETn1 / PETp1 | PCIe lane 1, host transmit pair |
| 39 | GND | Ground |
| 41 / 43 | PERn0 / PERp0 or SATA-B+ / SATA-B− | PCIe lane 0 host receive pair or SATA host receive pair |
| 45 | GND | Ground |
| 47 / 49 | PETn0 / PETp0 or SATA-A− / SATA-A+ | PCIe lane 0 host transmit pair or SATA host transmit pair |
| 51 | GND | Ground |
| 53 / 55 | REFCLKn / REFCLKp | PCIe differential reference clock |
| 57 | GND | Ground |
| 59–66 | — | Mechanical Key M notch; no contacts |
| 67 | Reserved / no connect | May be vendor-defined on a documented module; otherwise leave unconnected |
| 69 | CONFIG_1 / no connect | Open configuration strap for the conventional B+M storage assignment |
| 71 | GND | Ground |
| 73 | GND or VIO_CFG | Ground in the conventional assignment; optional I/O-voltage capability indication |
| 75 | GND / CONFIG_2 | Ground; also identifies the module configuration to a Key B host |
Bottom side
| Pin | Signal | Function |
|---|---|---|
| 2 / 4 | 3.3 V | Main module supply |
| 6 | Reserved / no connect | Leave unconnected in the conventional B+M storage assignment |
| 8 | PLN# or no connect | Optional power-loss notification in supported revisions |
| 10 | DAS/DSS# / LED_1# | Device activity, staggered spin-up disable, or activity-LED function |
| 12–19 | — | Mechanical Key B notch; no contacts |
| 20 / 22 / 24 / 26 / 28 | Reserved / no connect | Leave unconnected unless the applicable specification defines them |
| 30 | PLA_S3# or no connect | Optional power-loss acknowledgement in supported revisions |
| 32 / 34 / 36 | Reserved / no connect | Leave unconnected in the conventional storage assignment |
| 38 | DEVSLP or no connect | SATA device-sleep control; normally unused by a PCIe module |
| 40 | SMB_CLK | SMBus clock |
| 42 | SMB_DATA | SMBus data |
| 44 | ALERT# | Management-bus alert |
| 46 / 48 | Reserved / no connect | Leave unconnected unless the applicable specification defines them |
| 50 | PERST# | PCIe fundamental reset |
| 52 | CLKREQ# | PCIe reference-clock request |
| 54 | PEWAKE# | PCIe wake request |
| 56 / 58 | Reserved / manufacturing interface | Leave unconnected on the host unless explicitly documented |
| 59–66 | — | Mechanical Key M notch; no contacts |
| 68 | SUSCLK | Optional 32 kHz suspend clock |
| 70 / 72 / 74 | 3.3 V | Main module supply |
Signal groups
| Group | Pins | Notes |
|---|---|---|
| Power and ground | 2, 4, 70, 72, 74 and all assigned GND pins | 3.3 V main supply and ground returns |
| PCIe lane 0 / SATA | 41, 43, 47, 49 | Shared differential pairs; the module uses PCIe or SATA, never both simultaneously |
| PCIe lane 1 | 29, 31, 35, 37 | Second PCIe lane for an x2 link |
| PCIe clock and control | 50, 52–55 | Reset, clock request, wake, and 100 MHz reference clock |
| Management bus | 40, 42, 44 | SMBus clock, data, and alert |
| Storage control | 8, 10, 30, 38, 68 | Optional power-loss, activity, sleep, and suspend-clock functions |
| Configuration | 1, 21, 69, 75 | Straps used by a Key B host to identify the storage-module configuration |
The Key B notch removes contacts needed for PCIe lanes 2 and 3. Consequently, a B+M PCIe module is limited to x2, even when installed in a Key M socket that supports x4.
Electrical specifications
| Interface | Design value / requirement |
|---|---|
| Main power | Nominal 3.3 V on pins 2, 4, 70, 72, and 74 |
| PCIe pairs | 85 Ω differential nominal; place AC-coupling capacitors on each transmitter as required by PCIe |
| PCIe reference clock | 100 MHz differential clock when the common-clock architecture is used |
| SATA pairs | 100 Ω differential nominal |
| SMBus and sideband I/O | Logic level depends on the signal and specification revision; verify 1.8 V / 3.3 V compatibility |
| Active-low signals | Names ending in # are asserted low |
| Reserved / optional pins | Do not connect without confirming the current M.2 specification and both device datasheets |
Keep every high-speed pair short, impedance-controlled, and routed over a continuous reference plane. Match the two traces within each pair and avoid vias, stubs, plane gaps, switching nodes, and unnecessary layer changes.
Connector orientation
- The diagrams show the module contact edge, not the socket solder pads.
- The top/component side carries odd-numbered pins; the bottom side carries even-numbered pins.
- The Key B notch replaces positions 12–19, while the Key M notch replaces positions 59–66.
- A socket footprint may appear mirrored compared with the module. Follow the connector manufacturer’s recommended PCB footprint.
Common wiring configurations
PCIe x2 NVMe SSD
- Route PCIe lanes 0 and 1, REFCLK, PERST#, CLKREQ#, and PEWAKE# as required by the platform.
- Connect all specified 3.3 V and ground contacts and size the supply for the SSD’s peak current.
- In a Key M socket, expect at most x2 operation from the B+M module, not x4.
PCIe x1 device
- Route only lane 0 and its required clock and sideband signals.
- Confirm that the host firmware supports the device type and boot mode when used for storage.
SATA M.2 SSD
- Use the SATA alternate functions on pins 41, 43, 47, and 49.
- Implement DEVSLP and the configuration straps as required by the host and drive.
- Confirm SATA support explicitly: many Key M sockets are PCIe-only and many Key B sockets are intended only for WWAN modules.
Common mistakes
- Assuming that a B+M module supports both SATA and NVMe because it has two notches.
- Assuming that mechanical fit in either socket guarantees electrical compatibility or firmware support.
- Expecting PCIe x4 performance from a B+M module in a Key M socket.
- Using a WWAN-only Key B socket for a B+M SSD without checking SATA or PCIe routing.
- Swapping PET and PER or SATA A and B because signal names are read from the wrong perspective.
- Mirroring the footprint or confusing top-side and bottom-side contact numbers.
- Connecting reserved or manufacturing pins to platform signals.
- Ignoring SSD peak current, airflow, or thermal throttling.
Related connectors
| Connector | Typical use | Compatibility note |
|---|---|---|
| M.2 Key B | WWAN, SATA, PCIe x1/x2 | B+M modules fit mechanically, but operation depends on a shared storage interface |
| M.2 Key M | NVMe PCIe x4 and SATA storage | B+M modules fit mechanically but remain limited to PCIe x2 or SATA |
| M.2 Key A / A+E | Wireless connectivity | Different notches and pin assignments; not compatible with B+M storage modules |
| mSATA | Older SATA SSDs | Uses SATA but has a different connector and pinout |
All PCIe M.2 pinout pages
Compatibility guide · Key A · Key A+E · Key B · Key B+A · Key B+E · Key B+M · Key E · Key M
Official specifications
- PCI Express M.2 specification overview — PCI-SIG
- M.2 1.8 V sideband and power-loss enhancements — PCI-SIG
- PCI Express specifications — PCI-SIG
- NVM Express specifications — NVM Express
- Serial ATA specifications — SATA-IO
FAQ
Is B+M a separate socket type?
No. B+M describes a module with two notches. It is designed to fit mechanically in compatible Key B and Key M sockets.
Does every B+M SSD use SATA?
No. A B+M SSD may use SATA or PCIe/NVMe. The key shape alone does not identify the protocol.
Can a B+M NVMe SSD run at PCIe x4?
No. The Key B notch removes the contacts for lanes 2 and 3, so the module can expose at most two PCIe lanes.
Will a B+M SSD work in every Key B or Key M socket?
No. The socket must provide the same interface as the SSD, and the host firmware must support it.
Is the module hot-pluggable?
Do not assume it is. Power down the platform before inserting or removing a module unless the equipment documentation explicitly supports hot plugging.