PCIe M.2 — Key E Pinout
M.2 Key E is a 75-position Socket 1 connector mainly intended for wireless-connectivity modules. Depending on the host and module, it can expose PCIe, USB 2.0, SDIO, UART, PCM/I²S, I²C, and radio-control signals.
Compatibility warning: Key E describes the connector shape and pin map, not the interfaces actually wired by the host. CNVi/CNVio modules may use the same mechanical key but require a compatible Intel platform. Always check both the host and module documentation.
Connector overview
| Property | Value |
|---|---|
| Connector family | PCI Express M.2 / NGFF, Socket 1 |
| Key notch | Key E, positions 24 to 31 |
| Contacts | 75 positions; 67 electrical contacts with the Key E notch |
| Main use | Wi-Fi, Bluetooth, GNSS, NFC, and other wireless-connectivity modules |
| Possible host interfaces | 2 independent PCIe x1 links, USB 2.0, SDIO, UART, PCM/I²S, I²C |
| Main supply | 3.3 V |
Key E is not the normal connector for an M.2 NVMe SSD. Storage devices generally use Key M or Key B+M. Some wireless modules have an A+E edge key and can fit either socket, but electrical operation still depends on the interfaces wired by the host.
Pinout diagram
Top side — odd pins
Bottom side — even pins
Pin assignment table
Signal names use the host/platform perspective: PET is transmitted by the host toward the module, while PER is received by the host from the module. PCIe link 1 and several sideband functions are optional.
Color key: Power · Ground · USB · PCIe · SDIO / digital audio · I²C · Radio / platform control
Top side
| Pin | Signal | Function |
|---|---|---|
| 1 | GND | Ground |
| 3 / 5 | USB_D+ / USB_D− | USB 2.0 data pair, often used by Bluetooth |
| 7 | GND | Ground |
| 9 | SDIO_CLK / SYSCLK | SDIO clock or GNSS system clock |
| 11 | SDIO_CMD | SDIO command |
| 13 / 15 / 17 / 19 | SDIO_DATA0 / DATA1 / DATA2 / DATA3 | Four-bit SDIO data bus |
| 21 | SDIO_WAKE# | SDIO wake request |
| 23 | SDIO_RESET# / TX_BLANKING | SDIO reset or GNSS transmit-blanking input |
| 24–31 | — | Mechanical Key E notch; no contacts |
| 33 | GND | Ground |
| 35 / 37 | PETp0 / PETn0 | PCIe link 0, host transmit pair |
| 39 | GND | Ground |
| 41 / 43 | PERp0 / PERn0 | PCIe link 0, host receive pair |
| 45 | GND | Ground |
| 47 / 49 | REFCLKp0 / REFCLKn0 | PCIe link 0 differential reference clock |
| 51 | GND | Ground |
| 53 | CLKREQ0# | PCIe link 0 clock request |
| 55 | PEWAKE0# | PCIe link 0 wake request |
| 57 | GND | Ground |
| 59 / 61 | PETp1 / PETn1 | Optional PCIe link 1, host transmit pair |
| 63 | GND | Ground |
| 65 / 67 | PERp1 / PERn1 | Optional PCIe link 1, host receive pair |
| 69 | GND | Ground |
| 71 / 73 | REFCLKp1 / REFCLKn1 | Optional PCIe link 1 differential reference clock |
| 75 | GND | Ground |
Bottom side
| Pin | Signal | Function |
|---|---|---|
| 2 / 4 | 3.3 V | Main module supply |
| 6 | LED_1# | Open-drain status LED control |
| 8 | PCM_CLK / I2S_SCK | PCM or I²S serial clock |
| 10 | PCM_SYNC / I2S_WS | PCM frame sync or I²S word select |
| 12 | PCM_IN / I2S_SD_IN | PCM or I²S serial-data input |
| 14 | PCM_OUT / I2S_SD_OUT | PCM or I²S serial-data output |
| 16 | LED_2# | Open-drain status LED control |
| 18 | GND or VIO_CFG | Ground in the conventional assignment; optional I/O-voltage capability indication |
| 20 | UART_WAKE# | UART wake request |
| 22 | UART_RXD | UART receive data |
| 24–31 | — | Mechanical Key E notch; no contacts |
| 32 | UART_TXD | UART transmit data |
| 34 | UART_CTS | UART clear-to-send input |
| 36 | UART_RTS | UART request-to-send output |
| 38 / 40 / 42 | Vendor-defined | Use only when documented by both devices |
| 44 | COEX3 | Wireless-coexistence control |
| 46 | COEX_RXD | Wireless-coexistence receive |
| 48 | COEX_TXD | Wireless-coexistence transmit |
| 50 | SUSCLK | Optional 32 kHz suspend clock |
| 52 | PERST0# | PCIe link 0 reset |
| 54 | W_DISABLE2# / BT_DISABLE# | Disable radio function 2 or Bluetooth |
| 56 | W_DISABLE1# / WI-FI_DISABLE# | Disable radio function 1 or Wi-Fi |
| 58 | I2C_DATA | I²C data |
| 60 | I2C_CLK | I²C clock |
| 62 | ALERT# | I²C / platform alert |
| 64 | VIO 1.8 V or reserved | Optional 1.8 V I/O supply introduced by the Socket 1 enhancement |
| 66 | UIM_SWP / PERST1# | UIM single-wire protocol or optional PCIe link 1 reset |
| 68 | UIM_POWER_SNK / CLKREQ1# | UIM power sink or optional PCIe link 1 clock request |
| 70 | UIM_POWER_SRC / GPIO_1 / PEWAKE1# | UIM power source, GPIO, or optional PCIe link 1 wake request |
| 72 / 74 | 3.3 V | Main module supply |
Signal groups
| Group | Pins | Notes |
|---|---|---|
| Power and ground | 2, 4, 64, 72, 74 and all GND pins | 3.3 V main supply, optional 1.8 V I/O supply, and ground returns |
| USB 2.0 | 3, 5 | One bidirectional USB 2.0 link, often used by Bluetooth |
| SDIO | 9, 11, 13, 15, 17, 19, 21, 23 | Four-bit SDIO bus with clock, command, reset, and wake |
| PCM / I²S audio | 8, 10, 12, 14 | Digital audio clock, framing, input, and output |
| PCIe link 0 | 35, 37, 41, 43, 47, 49, 52, 53, 55 | PCIe x1 link with reference clock, reset, clock request, and wake |
| PCIe link 1 | 59, 61, 65–73 | Optional second PCIe x1 link; some control pins are shared with UIM/GPIO functions |
| UART | 20, 22, 32, 34, 36 | UART data, hardware flow control, and wake |
| I²C | 58, 60, 62 | 1.8 V management bus and alert |
| Radio control | 6, 16, 44, 46, 48, 50, 54, 56 | LEDs, disable controls, suspend clock, and coexistence |
The two PCIe groups are normally treated as independent x1 links. Do not assume that the host combines them into one x2 link or that link 1 is wired.
Electrical specifications
| Interface | Design value / requirement |
|---|---|
| Main power | Nominal 3.3 V on pins 2, 4, 72, and 74 |
| Optional I/O supply | 1.8 V VIO on pin 64 when supported; use VIO_CFG to verify module capability |
| PCIe pairs | 85 Ω differential nominal; place AC-coupling capacitors on each transmitter as required by PCIe |
| PCIe reference clock | 100 MHz differential clock when the common-clock architecture is used |
| USB 2.0 pair | 90 Ω differential nominal |
| SDIO, UART, I²C, and audio I/O | Commonly 1.8 V; verify the exact signaling voltage for the host and module |
| Active-low signals | Names ending in # are asserted low |
| Vendor / alternate pins | Do not connect without confirming the current M.2 specification and both device datasheets |
Keep every high-speed pair short, impedance-controlled, and routed over a continuous reference plane. Match the two traces within each pair and avoid vias, stubs, plane gaps, switching nodes, and unnecessary layer changes.
Connector orientation
- The diagrams show the module contact edge, not the socket solder pads.
- The top/component side carries odd-numbered pins; the bottom side carries even-numbered pins.
- Pin 1 is at the end opposite pin 75. The Key E notch replaces positions 24–31.
- A socket footprint may appear mirrored compared with the module. Follow the connector manufacturer’s recommended PCB footprint.
Common wiring configurations
Wi-Fi plus Bluetooth module
- Use PCIe link 0 for Wi-Fi and USB 2.0 on pins 3 and 5 for Bluetooth when specified by the module.
- Connect 3.3 V, every required ground, PERST0#, CLKREQ0#, and PEWAKE0#.
- Route W_DISABLE#, LED#, coexistence, and antenna-control signals only when required by the product.
SDIO wireless module
- Route the SDIO clock, command, four data lines, reset, and wake signals.
- Confirm the 1.8 V signaling domain and the allowed SDIO clock rate in both datasheets.
UART- or audio-enabled module
- Route UART or PCM/I²S only when the module documents those functions.
- Check signal direction, voltage domain, clock ownership, and whether pull-ups are required.
Dual-PCIe module
- Treat link 0 and link 1 as two independent x1 connections.
- Keep each link’s data pairs, clock, reset, clock-request, and wake signals with the matching link number.
Common mistakes
- Assuming that every physically fitting Key E or A+E module is electrically compatible.
- Treating an Intel CNVi/CNVio module as a standard PCIe/USB wireless module.
- Plugging a Key M or B+M SSD into a Key E connectivity socket.
- Treating the two PCIe x1 links as a guaranteed x2 link.
- Swapping PET and PER because the signal names are read from the module perspective instead of the host perspective.
- Mirroring the footprint or confusing top-side and bottom-side contact numbers.
- Driving 1.8 V SDIO, UART, I²C, or control signals with 3.3 V without checking tolerance.
- Connecting vendor-defined or alternate-function pins without checking the applicable specification revision.
Related connectors
| Connector | Typical use | Compatibility note |
|---|---|---|
| M.2 Key A / A+E | Wireless connectivity | An A+E module may fit either socket, but only shared, wired interfaces will work |
| M.2 Key B | WWAN, SATA, PCIe x2 | Different notch and pin assignment; not directly interchangeable |
| M.2 Key M | NVMe SSD, PCIe x4 | Storage-oriented connector; not compatible with Key E |
| Mini PCI Express | Older wireless cards | Different 52-pin connector and pinout; an active adapter may be required |
All PCIe M.2 pinout pages
Compatibility guide · Key A · Key A+E · Key B · Key B+A · Key B+E · Key B+M · Key E · Key M
Official specifications
- PCI Express M.2 specification overview — PCI-SIG
- M.2 Socket 1 enhancements — PCI-SIG
- PCI Express specifications — PCI-SIG
- USB specifications and documents — USB-IF
- I²C-bus specification and user manual — NXP
FAQ
Can a Key A module be installed in a Key E socket?
Only a module with a compatible A+E edge key can physically fit both. Electrical operation still depends on the interfaces wired by the host and used by the module.
Can a Key E socket accept an NVMe SSD?
Normally no. NVMe SSDs generally use Key M or B+M and require a storage-oriented socket.
Are both PCIe links always available?
No. The pinout provides two independent PCIe link groups, but a host may wire one, both, or neither.
Will an Intel CNVi/CNVio module work in any Key E socket?
No. CNVi/CNVio uses platform-specific connectivity and requires a compatible host chipset and socket implementation.
Is the connector hot-pluggable?
Do not assume it is. Power down the platform before inserting or removing a module unless the equipment documentation explicitly supports hot plugging.