PCIe M.2 — Key A+E Pinout
An M.2 Key A+E module has both the A and E notches so that it can fit mechanically in compatible Key A and Key E Socket 1 connectors. This dual-key arrangement is mainly used by Wi-Fi, Bluetooth, and other wireless-connectivity modules.
Compatibility warning: A+E describes the module’s two mechanical notches, not a distinct socket or a guaranteed electrical interface. The module and host must support the same PCIe, USB, and sideband signals. Intel CNVi/CNVio modules require a compatible platform even when they fit mechanically.
Connector overview
| Property | Value |
|---|---|
| Connector family | PCI Express M.2 / NGFF Socket 1 module edge |
| Key notches | Key A, positions 8 to 15; Key E, positions 24 to 31 |
| Contacts | 75 positions; 59 electrical contacts with both notches |
| Compatible sockets | Mechanically compatible with suitable Socket 1 Key A and Key E connectors |
| Main use | Wi-Fi, Bluetooth, GNSS, NFC, and other connectivity modules |
| Common interfaces | USB 2.0, PCIe x1, optional second PCIe x1 link, I²C, and radio-control signals |
| Main supply | 3.3 V |
There is no separate “A+E socket” in the usual M.2 connector family. The dual notches are placed on the module to broaden mechanical compatibility. They do not combine every interface assigned separately to Key A and Key E.
Pinout diagram
Top side — odd pins
Bottom side — even pins
Pin assignment table
Signal names use the host/platform perspective: PET is transmitted by the host toward the module, while PER is received by the host from the module. The table focuses on the common A+E connectivity mapping; contacts whose Key A and Key E functions conflict are left unused unless a module and host explicitly define them.
Color key: Power · Ground · USB · PCIe · I²C · Radio / platform control
Top side
| Pin | Signal | Function |
|---|---|---|
| 1 | GND | Ground |
| 3 / 5 | USB_D+ / USB_D− | USB 2.0 data pair, often used by Bluetooth |
| 7 | GND | Ground |
| 8–15 | — | Mechanical Key A notch; no contacts |
| 17 / 19 / 21 / 23 | Reserved / no connect | Key A and Key E assign different functions here; use only with an explicitly documented host and module |
| 24–31 | — | Mechanical Key E notch; no contacts |
| 33 | GND | Ground |
| 35 / 37 | PETp0 / PETn0 | PCIe link 0, host transmit pair |
| 39 | GND | Ground |
| 41 / 43 | PERp0 / PERn0 | PCIe link 0, host receive pair |
| 45 | GND | Ground |
| 47 / 49 | REFCLKp0 / REFCLKn0 | PCIe link 0 differential reference clock |
| 51 | GND | Ground |
| 53 | CLKREQ0# | PCIe link 0 clock request |
| 55 | PEWAKE0# | PCIe link 0 wake request |
| 57 | GND | Ground |
| 59 / 61 | PETp1 / PETn1 | Optional PCIe link 1, host transmit pair |
| 63 | GND | Ground |
| 65 / 67 | PERp1 / PERn1 | Optional PCIe link 1, host receive pair |
| 69 | GND | Ground |
| 71 / 73 | REFCLKp1 / REFCLKn1 | Optional PCIe link 1 differential reference clock |
| 75 | GND | Ground |
Bottom side
| Pin | Signal | Function |
|---|---|---|
| 2 / 4 | 3.3 V | Main module supply |
| 6 | LED_1# | Open-drain status LED control |
| 8–15 | — | Mechanical Key A notch; no contacts |
| 16 | LED_2# | Open-drain status LED control |
| 18 | VIO_CFG or legacy ground | Optional indication of the module’s I/O-voltage capability |
| 20 / 22 | Reserved / no connect | Key A and Key E assign different functions here; use only when both devices document them |
| 24–31 | — | Mechanical Key E notch; no contacts |
| 32 / 34 / 36 | Reserved / no connect | Key A and Key E assign different functions here; use only when both devices document them |
| 38 / 40 / 42 | Vendor-defined | Leave unconnected unless the host and module define a shared function |
| 44 | COEX3 | Wireless-coexistence control |
| 46 | COEX_RXD | Wireless-coexistence receive |
| 48 | COEX_TXD | Wireless-coexistence transmit |
| 50 | SUSCLK | Optional 32 kHz suspend clock |
| 52 | PERST0# | PCIe link 0 reset |
| 54 | W_DISABLE2# / BT_DISABLE# | Disable radio function 2 or Bluetooth |
| 56 | W_DISABLE1# / WI-FI_DISABLE# | Disable radio function 1 or Wi-Fi |
| 58 | I2C_DATA | I²C data |
| 60 | I2C_CLK | I²C clock |
| 62 | ALERT# | I²C / platform alert |
| 64 | VIO 1.8 V or reserved | Optional 1.8 V I/O supply introduced by the Socket 1 enhancement |
| 66 | PERST1# or alternate function | Optional PCIe link 1 reset |
| 68 | CLKREQ1# or alternate function | Optional PCIe link 1 clock request |
| 70 | PEWAKE1# or alternate function | Optional PCIe link 1 wake request |
| 72 / 74 | 3.3 V | Main module supply |
Signal groups
| Group | Pins | Notes |
|---|---|---|
| Power and ground | 2, 4, 64, 72, 74 and all GND pins | 3.3 V main supply, optional 1.8 V I/O supply, and ground returns |
| USB 2.0 | 3, 5 | One bidirectional USB 2.0 link, often used by Bluetooth |
| PCIe link 0 | 35, 37, 41, 43, 47, 49, 52, 53, 55 | PCIe x1 link with reference clock, reset, clock request, and wake |
| PCIe link 1 | 59, 61, 65–73 | Optional second PCIe x1 link; control pins may have alternate UIM/GPIO functions |
| I²C | 58, 60, 62 | 1.8 V management bus and alert |
| Radio control | 6, 16, 44, 46, 48, 50, 54, 56 | LEDs, disable controls, suspend clock, and coexistence |
| Socket-specific area | 17–23, 32, 34, 36, 38, 40, 42 | Key A and Key E assignments differ; portable A+E modules normally avoid these contacts |
The two PCIe groups are normally treated as independent x1 links. Do not assume that the host combines them into one x2 link or that every A/E socket wires the optional link 1.
Electrical specifications
| Interface | Design value / requirement |
|---|---|
| Main power | Nominal 3.3 V on pins 2, 4, 72, and 74 |
| Optional I/O supply | 1.8 V VIO on pin 64 when supported; use VIO_CFG to verify module capability |
| PCIe pairs | 85 Ω differential nominal; place AC-coupling capacitors on each transmitter as required by PCIe |
| PCIe reference clock | 100 MHz differential clock when the common-clock architecture is used |
| USB 2.0 pair | 90 Ω differential nominal |
| I²C and radio-control I/O | Commonly 1.8 V or 3.3 V, depending on the signal and specification revision |
| Active-low signals | Names ending in # are asserted low |
| Reserved / vendor pins | Do not connect without confirming the current M.2 specification and both device datasheets |
Keep every high-speed pair short, impedance-controlled, and routed over a continuous reference plane. Match the two traces within each pair and avoid vias, stubs, plane gaps, switching nodes, and unnecessary layer changes.
Connector orientation
- The diagrams show the module contact edge, not the socket solder pads.
- The top/component side carries odd-numbered pins; the bottom side carries even-numbered pins.
- The Key A notch replaces positions 8–15, while the Key E notch replaces positions 24–31.
- A socket footprint may appear mirrored compared with the module. Follow the connector manufacturer’s recommended PCB footprint.
Common wiring configurations
Wi-Fi plus Bluetooth module
- Use PCIe link 0 for Wi-Fi and USB 2.0 on pins 3 and 5 for Bluetooth when specified by the module.
- Connect 3.3 V, every required ground, PERST0#, CLKREQ0#, and PEWAKE0#.
- Route W_DISABLE#, LED#, coexistence, and I²C only when required by the product.
PCIe-only wireless module
- Route the implemented PCIe link, its reference clock, reset, clock-request, and wake signals.
- Do not assume that USB is unused simply because Wi-Fi uses PCIe; a second function may still require USB 2.0.
Module with two PCIe functions
- Treat link 0 and link 1 as two independent x1 connections.
- Confirm that both the chosen socket and module implement the second clock and sideband group.
Common mistakes
- Assuming that two notches make every Key A and Key E signal available to the module.
- Assuming that mechanical fit guarantees the required PCIe, USB, or sideband wiring.
- Treating an Intel CNVi/CNVio module as a standard PCIe/USB wireless module.
- Treating the two PCIe x1 links as a guaranteed x2 link.
- Using socket-specific DisplayPort, SDIO, audio, or UART contacts without support from both devices.
- Swapping PET and PER because the signal names are read from the module perspective instead of the host perspective.
- Mirroring the footprint or confusing top-side and bottom-side contact numbers.
- Driving 1.8 V management signals with 3.3 V without checking tolerance.
Related connectors
| Connector | Typical use | Compatibility note |
|---|---|---|
| M.2 Key A | Wireless and display connectivity | A+E modules fit mechanically, but only their Key A-compatible signals can operate |
| M.2 Key E | Wireless connectivity | A+E modules fit mechanically, but only their Key E-compatible signals can operate |
| M.2 Key B / B+M | WWAN and storage | Different notches and pin assignments; not interchangeable with A+E |
| M.2 Key M | NVMe SSD and PCIe x4 storage | Storage-oriented connector; incompatible with A+E modules |
All PCIe M.2 pinout pages
Compatibility guide · Key A · Key A+E · Key B · Key B+A · Key B+E · Key B+M · Key E · Key M
Official specifications
- PCI Express M.2 specification overview — PCI-SIG
- M.2 Socket 1 enhancements for Keys E and A+E — PCI-SIG
- PCI Express specifications — PCI-SIG
- USB specifications and documents — USB-IF
- I²C-bus specification and user manual — NXP
FAQ
Is A+E a separate socket type?
No. A+E describes a module with two notches. It is designed to fit mechanically in compatible Key A and Key E sockets.
Will an A+E Wi-Fi card work in every Key A or Key E socket?
No. The socket must provide the PCIe, USB, and control signals required by the card, and the host firmware must support it.
Are DisplayPort and SDIO available on a generic A+E module?
Not normally. Those functions use contacts whose assignments differ between Key A and Key E. Use them only when the host and module explicitly document the same mapping.
Will an Intel CNVi/CNVio module work in any A or E socket?
No. CNVi/CNVio uses platform-specific connectivity and requires a compatible host chipset and socket implementation.
Is the module hot-pluggable?
Do not assume it is. Power down the platform before inserting or removing a module unless the equipment documentation explicitly supports hot plugging.