FundamentalsSignals & Interfaces

TTL and CMOS logic levels

Understand VIL, VIH, VOL, and VOH, verify noise margins, and design safe interfaces between 1.8 V, 3.3 V, and 5 V domains.

Level

Intermediate

Reading time

15 min

Primary standard or source

Texas Instruments and Nexperia logic guides, and component datasheets

Last verified

13 September 2026

Associated tool

Pull-up / Pull-down Calculator

Written and technically reviewed byElectroDesignForge Engineering Team

View the editorial process

Key point: an output is compatible with an input only when its worst-case guaranteed levels meet that input’s thresholds across supply, temperature, and load current. A nominal 1.8 V, 3.3 V, or 5 V label alone is not enough.

Quick reference

The region between V_IL,max and V_IH,min is undefined for a digital input. It is not a usable control level.

1. Inputs and outputs: keep the four specifications separate

I means input and O means output. Input limits say what a receiver accepts; output limits say what a driver guarantees.

Use guaranteed min/max limits, not typical plots, to design an interface. V_OH may be close to V_DD with no load, yet fall materially when the output sources current.

Static noise margins

NMH = VOH(min, driver) − VIH(min, receiver)
NML = VIL(max, receiver) − VOL(max, driver)

Both margins must be positive. Larger margins tolerate more noise, ground shift, cable drop, and part variation. They do not replace checking rise time, capacitive loading, and absolute maximum ratings.

2. CMOS thresholds: often supply-relative

Many conventional CMOS families specify input thresholds near:

VIL(max) ≈ 0.3 × VDD
VIH(min) ≈ 0.7 × VDD

This is a useful rule of thumb, not a universal requirement. Modern CMOS may use fixed thresholds, TTL-compatible inputs, Schmitt triggers, or dedicated I/O standards.

A 3.3 V CMOS output therefore cannot normally guarantee the HIGH required by a 5 V, 0.7 × V_DD CMOS input. Conversely, a 5 V output can exceed a 3.3 V input’s electrical limit even when its logic level is easy to read.

3. TTL: why 3.3 V can work, but is not a universal rule

Historic 5 V bipolar TTL typically uses fixed input limits: V_IL,max = 0.8 V and V_IH,min = 2.0 V. A 74LS HIGH output may only be guaranteed to 2.7 V under its stated light load, while a LOW output can be guaranteed up to about 0.4 or 0.5 V at the stated current.

Many modern “TTL-compatible” or LVTTL devices retain the 2.0 V HIGH threshold while operating from 3.3 V. TTL in an I/O table then describes the thresholds, not necessarily the internal technology or 5 V tolerance.

4. 1.8 V, 3.3 V, and 5 V compatibility

The following assumes a push-pull output and an ordinary input. Treat it as a starting point; the two actual datasheets decide the design.

Two independent checks

1. Logic compatibility: compare V_OH,min with V_IH,min, and V_OL,max with V_IL,max.
2. Electrical compatibility: check V_IN,max, absolute maximum ratings, pin currents, and the condition when the receiver is unpowered.

An input labelled “5 V tolerant” addresses only part of the electrical question. It does not by itself guarantee threshold compatibility, power-off injection behaviour, or tolerance in every pin mode.

5. Worked example: 3.3 V GPIO to a 5 V TTL input

Suppose a GPIO guarantees V_OH,min = 2.9 V at the selected load and V_OL,max = 0.4 V. The TTL input requires V_IH,min = 2.0 V and accepts V_IL,max = 0.8 V.

NMH = 2.9 V − 2.0 V = 0.9 V
NML = 0.8 V − 0.4 V = 0.4 V

Both margins are positive, so the logic levels are compatible. Still check that the TTL pin has no pull-up to 5 V and no input-current condition that back-powers the GPIO while it is off. A 3.3 V GPIO is not automatically safe with a resistor pulled to 5 V.

6. Pull-ups, open drain, and the pull resistor

An open-drain output actively drives only LOW. A pull-up resistor creates HIGH, so its rail determines both the HIGH level and the overvoltage risk.

For pull-up R_P to V_PU with total leakage I_leak, a first HIGH bound is:

VHIGH ≈ VPU − Ileak × RP
RP(max) ≤ (VPU − VIH(min)) / Ileak

The LOW bound comes from current when the line is pulled down:

RP(min) ≥ (VPU − VOL(max)) / IOL(max)

Then check RC rise time. Too large a resistor gives a slow edge; too small a resistor increases LOW-state current. Use the Pull-up / Pull-down Calculator to size the range from thresholds, GPIO current, capacitance, and rise-time target.

Do not improvise these cases

• A 5 V pull-up on a 3.3 V pin is permitted only when that exact pin and mode are explicitly 5 V tolerant, including when unpowered.
• Push-pull outputs must not be tied together. Wired logic needs compatible open outputs.
• A Schmitt input helps with slow edges but does not make an overvoltage safe.
• Bidirectional MOSFET translators suit some open-drain buses, not push-pull high-speed signals without timing analysis.

7. Schematic and prototype verification method

1. Identify every exact pin type: input, push-pull, open drain, Schmitt, analogue, strap, or special-tolerance input.
2. Extract guaranteed V_IL, V_IH, V_OL, and V_OH at the product’s supply, temperature, and current.
3. Calculate NMH and NML; a negative margin requires translation or a different architecture.
4. Check V_IN,max, absolute maximum ratings, protection diodes, and partial-power-down behaviour.
5. Include internal and external pull resistors in the current path. Parallel resistors and opposite rails can produce an intermediate level.
6. Measure at the receiver with an appropriate probe: edge shape, overshoot, ground bounce, minimum V_OH, and maximum V_OL at real load.

Common pitfalls

Associated tool

Open the Pull-up / Pull-down Calculator to find a resistor range consistent with logic thresholds, GPIO current, line capacitance, and rise time.

Sources

• Texas Instruments — Logic Guide and 74xx/LVC/AHC family datasheets.
• Nexperia — application notes and CMOS / TTL-compatible logic family datasheets.
• The two actual component datasheets: DC electrical-characteristics tables, absolute maximum ratings, and power-sequencing requirements.