Pull-up / Pull-down Calculator
Size a pull resistor from GPIO current, logic thresholds, line capacitance and timing. Compare practical E-series values before committing a schematic.
Line configuration
Passive HIGH; an output or switch actively sinks the LOW state.
Logic and GPIO limits
Line and target
Generic timing budget: 30% of the entered period. Use the interface datasheet when it specifies a tighter edge limit.
Safe resistance window
The desired resistor is inside the current and timing window, and both static logic levels pass.
A nominal resistor can satisfy both first-pass constraints.
Safe E-series choices
Static levels pass
Tolerance map: frequency × line capacitance
A first-pass nine-corner sweep. Each cell shows the safe E24 pick at that frequency/capacitance corner; click it to inspect the result.
This is a first-pass RC model. Include every pin, trace, cable and probe in the line capacitance, then validate leakage, resistor tolerance, output resistance, supply range, EMC and the selected device datasheets.
Digital-interface guide
Choose a pull-up or pull-down resistor that holds the line
A bias resistor does more than set a default state. Too small, it overloads the driver forcing the opposite state; too large, line capacitance slows the edge. This tool connects both limits to an actually purchasable value.
Method and assumptions
Rmin is calculated from the entered GPIO-current limit, deliberately conservatively. Rmax comes from the RC network crossing the logic threshold; in I²C, the tool applies the 30–70% rise-time convention to the selected Sm, Fm, Fm+, Hs, or UFm profile. Hs warns when the controller’s active rise assist must be verified, while UFm explains that a passive pull-up does not apply. LineScope then sweeps frequency and capacitance around the nominal point to make margin visible.
Inputs to verify
Datasheet limits
Enter VOL(max), VOH(min), VIL(max), VIH(min), and the appropriate current limit. Do not mix source and sink capabilities: they often differ for the same GPIO.
Capacitance truly seen by the line
Add pins, traces, cables, connectors, and probes. An oscilloscope probe, remote module, or cable can easily dominate the trace capacitance you expected.
Recommended workflow
- 1Choose the mode: pull-up, pull-down, open drain, a GPIO that may float, or I²C. In I²C, then choose Sm, Fm, Fm+, Hs, or UFm; the profile automatically sets its frequency and rise-time budget.
- 2Read the Rmin–Rmax window, then test the suggested E12, E24, or E96 value that best matches your sourcing.
- 3Click the harshest LineScope corners, then validate tolerance, leakage, temperature, supply, and edge shape on real hardware.
How to read an example
At 3.3 V with 3 mA GPIO current and 100 pF, a 4.7 kΩ resistor can leave a comfortable window at 100 kHz. If a cable doubles capacitance and the bus moves to 400 kHz, LineScope may show that the same value no longer meets the rise-time limit; a lower resistance or reduced capacitance is then needed.
What this calculation does not replace
The model is a first-pass RC screen. It does not model leakage, pull resistors already fitted on modules, resistor tolerance, VCC min/max range, transistor dynamic resistance, noise, EMC, or the details of an Hs controller with an active current source. UFm is treated as a unidirectional push-pull bus with no passive bias resistor.
Frequently asked questions
Why does Rmin use VCC rather than only VCC − VOL?
The calculator treats entered GPIO current as an absolute limit and therefore chooses a cautious bound. If you use an IOL guaranteed at a specified VOL, always compare that exact condition with the driver datasheet.
Why does I²C not simply use 30% of the period?
I²C defines separate rise-time limits by bus mode. They apply between 30% and 70% of the rail, which is why the tool shows the 0.8473RC constant in this mode.
References to consult
- Method references: GPIO and receiver-input datasheets; the relevant I²C specification for bus capacitance, IOL, and rise-time limits; and EIA/IEC 60063 for preferred-value series.
- For any off-board or critical interface, also verify levels at worst-case temperature and supply with a low-capacitance probe.
Original educational content, reviewed for technical clarity on 20 August 2026. Always verify datasheets, applicable standards, and your design before power-up or manufacture.